There is a bug in the R0200J3 ACPI DSDT. It erroneously defines the PCI Configuration Space register TOLUD for the PCI root bridge (\_SB.PCI0.(HBUS.)TOUD) as 6 bits wide instead of 5. This register reports the address of the top of usable RAM which is used in \_SB.PCI0._CRS() to return a package to the host that includes the calculated size of RAM in the DWordRange ResourceProducer AddressRangeMemory \_SB.PCI0.BUF0._X0D.
OperationRegion (HBUS, PCI_Config, 0x40, 0xC0)
Field (HBUS, DWordAcc, NoLock, Preserve)
{
// ...
Offset (0x5C), // 0x5C + base 0x40 = offset 0x9C in PCI Config
, 3,
TOUD, 6 // Intel Mobile 945 Express TOLUD register
}
// ...
Method (_CRS, 0, Serialized)
{
// ...
CreateDWordField (BUF0, \_SB.PCI0._X0D._MIN, M1MN)
CreateDWordField (BUF0, \_SB.PCI0._X0D._MAX, M1MX)
CreateDWordField (BUF0, \_SB.PCI0._X0D._LEN, M1LN)
ShiftLeft (TOUD, 0x1B, M1MN)
Add (Subtract (M1MX, M1MN), One, M1LN)
Return (BUF0)
}
PCIO is the root bridge in the Mobile Intel® 945 Express Chip-set. According to the data-sheet at 5.1.26:
TOLUD - Top of Low Used DRAM Register - bits 7:3
B/D/F/Type: 0/0/0/PCI
Address Offset: 9Ch
Default Value: 08h
Access: R/W/L; RO
Size: 8 bits
This 8-bit register defines the Top of Usable Dram. Graphics Stolen Memory and TSEG
are within dram space defined under TOLUD. From the top of low used dram, (G)MCH
claims 1 to 64 MBs of DRAM for internal graphics if enabled and 1, 2 or 8 MBs of DRAM
for TSEG if enabled.
Depending on how the host OS ACPI core interprets the Field FieldUnit declarations, this could result in a bit from the following register, SMRAM, being interpreted as part of the TOLUD value. If the interpreter discards illegal bit-widths the entire register (value) could be ignored.
