topic BIOS R0200J3 BUG in ACPI DSDT TO(L)UD definition in PCs & Accessories https://community.sony.ie/t5/pcs-accessories/bios-r0200j3-bug-in-acpi-dsdt-to-l-ud-definition/m-p/45695#M59428 <HTML><HEAD></HEAD><BODY><P>There is a bug in the R0200J3 ACPI DSDT. It erroneously defines the PCI Configuration Space register TOLUD for the PCI root bridge (\_SB.PCI0.(HBUS.)TOUD) as 6 bits wide instead of 5. This register reports the address of the top of usable RAM which is used in \_SB.PCI0._CRS() to return a package to the host that includes the calculated size of RAM in the DWordRange ResourceProducer AddressRangeMemory \_SB.PCI0.BUF0._X0D.<BR /><BR /><PRE>OperationRegion (HBUS, PCI_Config, 0x40, 0xC0)<BR />Field (HBUS, DWordAcc, NoLock, Preserve)<BR />{<BR /> // ... <BR /> Offset (0x5C), // 0x5C + base 0x40 = offset 0x9C in PCI Config<BR /> , 3, <BR /> TOUD, 6 // Intel Mobile 945 Express TOLUD register<BR />}<BR /><BR />// ...<BR /><BR />Method (_CRS, 0, Serialized)<BR />{<BR /> // ...<BR /> CreateDWordField (BUF0, \_SB.PCI0._X0D._MIN, M1MN)<BR /> CreateDWordField (BUF0, \_SB.PCI0._X0D._MAX, M1MX)<BR /> CreateDWordField (BUF0, \_SB.PCI0._X0D._LEN, M1LN)<BR /> ShiftLeft (TOUD, 0x1B, M1MN)<BR /> Add (Subtract (M1MX, M1MN), One, M1LN)<BR /> Return (BUF0)<BR />}<BR /></PRE><BR />PCIO is the root bridge in the Mobile Intel® 945 Express Chip-set. According to the data-sheet at 5.1.26:<BR /><PRE __jive_macro_name="quote" class="jive_text_macro jive_macro_quote">TOLUD - Top of Low Used DRAM Register - bits 7:3<BR /><BR />B/D/F/Type: 0/0/0/PCI<BR />Address Offset: 9Ch<BR />Default Value: 08h<BR />Access: R/W/L; RO<BR />Size: 8 bits<BR /><BR />This 8-bit register defines the Top of Usable Dram. Graphics Stolen Memory and TSEG<BR />are within dram space defined under TOLUD. From the top of low used dram, (G)MCH<BR />claims 1 to 64 MBs of DRAM for internal graphics if enabled and 1, 2 or 8 MBs of DRAM<BR />for TSEG if enabled.<BR /></PRE><BR /><BR />Depending on how the host OS ACPI core interprets the Field FieldUnit declarations, this could result in a bit from the following register, SMRAM, being interpreted as part of the TOLUD value. If the interpreter discards illegal bit-widths the entire register (value) could be ignored.<BR /></P></BODY></HTML> Fri, 18 Jul 2008 18:30:47 GMT IntuitiveNipple 2008-07-18T18:30:47Z BIOS R0200J3 BUG in ACPI DSDT TO(L)UD definition https://community.sony.ie/t5/pcs-accessories/bios-r0200j3-bug-in-acpi-dsdt-to-l-ud-definition/m-p/45695#M59428 <HTML><HEAD></HEAD><BODY><P>There is a bug in the R0200J3 ACPI DSDT. It erroneously defines the PCI Configuration Space register TOLUD for the PCI root bridge (\_SB.PCI0.(HBUS.)TOUD) as 6 bits wide instead of 5. This register reports the address of the top of usable RAM which is used in \_SB.PCI0._CRS() to return a package to the host that includes the calculated size of RAM in the DWordRange ResourceProducer AddressRangeMemory \_SB.PCI0.BUF0._X0D.<BR /><BR /><PRE>OperationRegion (HBUS, PCI_Config, 0x40, 0xC0)<BR />Field (HBUS, DWordAcc, NoLock, Preserve)<BR />{<BR /> // ... <BR /> Offset (0x5C), // 0x5C + base 0x40 = offset 0x9C in PCI Config<BR /> , 3, <BR /> TOUD, 6 // Intel Mobile 945 Express TOLUD register<BR />}<BR /><BR />// ...<BR /><BR />Method (_CRS, 0, Serialized)<BR />{<BR /> // ...<BR /> CreateDWordField (BUF0, \_SB.PCI0._X0D._MIN, M1MN)<BR /> CreateDWordField (BUF0, \_SB.PCI0._X0D._MAX, M1MX)<BR /> CreateDWordField (BUF0, \_SB.PCI0._X0D._LEN, M1LN)<BR /> ShiftLeft (TOUD, 0x1B, M1MN)<BR /> Add (Subtract (M1MX, M1MN), One, M1LN)<BR /> Return (BUF0)<BR />}<BR /></PRE><BR />PCIO is the root bridge in the Mobile Intel® 945 Express Chip-set. According to the data-sheet at 5.1.26:<BR /><PRE __jive_macro_name="quote" class="jive_text_macro jive_macro_quote">TOLUD - Top of Low Used DRAM Register - bits 7:3<BR /><BR />B/D/F/Type: 0/0/0/PCI<BR />Address Offset: 9Ch<BR />Default Value: 08h<BR />Access: R/W/L; RO<BR />Size: 8 bits<BR /><BR />This 8-bit register defines the Top of Usable Dram. Graphics Stolen Memory and TSEG<BR />are within dram space defined under TOLUD. From the top of low used dram, (G)MCH<BR />claims 1 to 64 MBs of DRAM for internal graphics if enabled and 1, 2 or 8 MBs of DRAM<BR />for TSEG if enabled.<BR /></PRE><BR /><BR />Depending on how the host OS ACPI core interprets the Field FieldUnit declarations, this could result in a bit from the following register, SMRAM, being interpreted as part of the TOLUD value. If the interpreter discards illegal bit-widths the entire register (value) could be ignored.<BR /></P></BODY></HTML> Fri, 18 Jul 2008 18:30:47 GMT https://community.sony.ie/t5/pcs-accessories/bios-r0200j3-bug-in-acpi-dsdt-to-l-ud-definition/m-p/45695#M59428 IntuitiveNipple 2008-07-18T18:30:47Z